The semiconductor industry has experienced technological advances that have permitted increases in density and/or complexity of semiconductor memory devices. Also, the technological advances have allowed decreases in power consumption and package sizes of various types of semiconductor memory devices. There is a continuing trend to employ and/or fabricate advanced semiconductor memory devices using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Semiconductor-on-insulator (SOI) and bulk substrates are examples of materials that may be used to fabricate such semiconductor memory devices. Such semiconductor memory devices may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET devices.
A semiconductor memory device may include a memory cell having a memory transistor with an electrically floating body region wherein electrical charges may be stored. The electrical charges stored in the electrically floating body region may represent a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state). Also, a semiconductor memory device may be fabricated on semiconductor-on-insulator (SOI) substrates or bulk substrates (e.g., enabling body isolation). For example, a semiconductor memory device may be fabricated as a three-dimensional (3-D) device (e.g., multiple gate devices, Fin-FETs, recessed gates and pillars).
In one conventional technique, an array of minimum feature size memory cells may print uniformly in accordance with certain lithographic specifications while the periodicity of a lithographic pattern remains consistent. When the periodicity of the lithographic pattern is interrupted (e.g., at an edge of the array), however, the minimum feature size memory cells may not print uniformly.
In another conventional technique, a storage array of minimum feature size memory cells may use dummy pillar structures to ensure proper printing of active pillar structures near an array edge when the periodicity of a lithographic pattern is interrupted to form a bottom contact to buried diffusion. These dummy pillar structures may be similar to active pillar structures in physical appearance, but may not contribute to any storage function of the array. Likewise, if, for example, the bottom contact to buried diffusion is nested within an array of pillar structures, dummy pillar structures may be formed on both sides of the nested bottom contact to buried diffusion to provide for proper printing of adjacent active pillar structures.
Often, the conventional use of dummy pillar structures may significantly increase area overhead of the array since, for example, two (2) rows of dummy pillar structures may be formed between a row of bottom contacts to buried diffusion and an array of active pillar structures. In certain instances, the area overhead attributed to the use of dummy pillar structures may double when the bottom contacts to buried diffusion are nested within an array of pillar structures. In such instances, for example, two (2) rows of dummy pillar structures may be formed on both sides of the nested bottom contacts. Also, the conventional use of dummy pillar structures may significantly increase the processing cost and complexity of forming array edges that include separate pillar bottom contacts to buried diffusion.
In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with the conventional use of conventional dummy pillar structures.